R&D Altanova, a leading provider of test interface solutions to the largest integrated device manufacturers, fabless semicons and semicon foundries, supports 5G, AI, radar, autonomous vehicles and IoT with Uyemura’s reduction-assisted gold process.
Uniform, corrosion-free deposits, tight pitch /spacing capability and excellent thru-hole plating are key advantages.
R&D ALTANOVA ANNOUNCES PROMOTION OF SEYED PARANSUN TO CEO
SOUTH PLAINFIELD, N.J. – March 7, 2017
Seyed Paransun, CEO & President of R&D Altanova
R&D Altanova, Inc. (www.rdaltanova.com), the leading provider of full turn-key test interface solutions, announced that its Board of Directors has unanimously appointed Seyed Paransun as Chief Executive Officer. Seyed will assume the role of CEO immediately and continue to serve as the Company’s President. James Russell will assume the role of Executive Chairman of the Board providing ongoing executive and technical guidance and Board-level leadership.
“Seyed joined R&D in 2016 and in a short period of time has proven to be a visionary leader with superb execution abilities. We are confident Seyed’s technology background and business experience is well suited to lead the next phase of the company’s growth and success”, said David Belluck, a board member of R&D Altanova and a General Partner at Riverside Partners.
Seyed has an extensive background in the semiconductor and electronics industry. He is best known for his ability to lead change and transform businesses for increased productivity and profitability. Prior to Joining R&D Altanova, Seyed served as Vice President of worldwide back-end operations and operations excellence at Atmel Corporation with responsibilities for both US and Asia facilities. Seyed has also held various executive positions including Vice President and General Manager at NXP as well as Senior Vice President of Test Services at Amkor Technology.
“I am honored to have been chosen by the board to lead R&D Altanova,” Seyed said. “I firmly believe that we can rely on our innovative and customer centric mindset to push boundaries and surpass our goals. We will continue to focus our investments in our employees and in the development of industry leading technology to ensure we can support our customers’ most ambitious technology road maps. I look forward to working with our executive team and our employees in serving our customers and driving growth for our company.”
In his role as Executive Chairman, Mr. Russell remains an employee of the company and will help with its technical strategy and direction. “I am very proud of what we have accomplished during my time as CEO and look forward to being part of the company’s continued success,” added Mr. Russell. “I want to congratulate Seyed on his promotion. I have the utmost confidence that Seyed and the rest of the management team will continue to drive technical and business expansion, ensuring the future success of R&D Altanova.”
About R&D Altanova, Inc.
Celebrating over forty years of excellence in leading-edge, technology driven, quick-turn PWB manufacturing, R&D Altanova specializes in advanced automated test environment interface boards for the semi-conductor test market. Solutions include the simulation, design, layout, fabrication, and component & mechanical assembly of test interface boards.
With offices in New Jersey, California, Pennsylvania, Arizona, Costa Rica, Southeast Asia, Shanghai and Taiwan, R&D Altanova is the leading provider of full turn-key test interface solutions to many of the world’s largest integrated device manufacturers, fabless semiconductor companies and semiconductor foundries. Learn more at www.rdaltanova.com
R&D ALTANOVA ANNOUNCES NEW PRESIDENT SEYED PARANSUN
SOUTH PLAINFIELD, N.J. – September 8, 2016
R&D Altanova, Inc. (www.rdaltanova.com), the leading provider of full turn-key test interface solutions, announced this week that it has appointed Seyed Paransun as President, responsible for worldwide operations as well as overall company P&L. Seyed will also join the R&D Altanova Board as a director.
Seyed has an extensive background in the semiconductor and electronics industry. He is best known for his ability to lead change and transform businesses for increased productivity and profitability. Most recently, Seyed served as Vice President of worldwide back end operations and operations excellence at Atmel Corporation with responsibilities for US and Asia facilities. Prior to Atmel, Seyed was the Vice President and General Manager at NXP, managing the sensors and actuators division with full responsibility for product development, marketing, R&D and divisional P&L. In addition, as Senior Vice President of Test Services at Amkor Technology, Seyed managed Amkor’s test business responsible for sales, marketing, supplier management, and aggregate P&L for all six test factories as well as technology development centers in the U.S. and Asia.
“Seyed comes to the company with over 30 years of semiconductor experience and a successful track record in test and international operations, said James Russell, CEO of R&D Altanova. “I am confident in Seyed’s ability to help lead R&D Altanova into our next phase of growth internationally.”
“I’m honored to join R&D Altanova and have the opportunity to leverage RDA’s decades of technology innovation and expand our differentiated value propositions to the broader market place,” added Seyed. “I look forward to working alongside R&D Altanova’s leaders, talented employees, and loyal partners to push the boundaries, build on our core business, drive profitable growth and embrace operational excellence. Together we will continue to collaborate with our customers and develop new solutions addressing the challenges of finer geometries and higher speeds while supporting aggressive time to market timelines.”
About R&D Altanova, Inc.
Celebrating over forty years of excellence in leading-edge, technology driven, quick-turn PWB manufacturing, R&D Altanova specializes in advanced automated test environment interface boards for the semi-conductor test market. Solutions include the simulation, design, layout, fabrication, and component & mechanical assembly of test interface boards.
With offices in New Jersey, California, Pennsylvania, Arizona, Costa Rica, Southeast Asia, and Taiwan, R&D Altanova is the leading provider of full turn-key test interface solutions to many of the world’s largest integrated device manufacturers, fabless semiconductor companies and semiconductor foundries. Learn more at www.rdaltanova.com
Don Thompson, Director of Engineering at R&D Altanova, along with Jose Moreira (Advantest) have received yet another award for their presentation “Designing Sockets for Ludicrous Speed (80 GHZ)”.
Best ATE Paper of 2015
The presentation has been selected as the Best ATE Paper Award for 2015. This award was created by Test Vision 2020 and the IEEE Test Technology Council to recognize the most influential ATE paper of the year.
This presentation was also previously awarded “Best Paper/Presentation” at BITS 2015.
The presentation can be found by accessing our White Papers & Presentations page.
Carol McCuen, an RF/Microwave engineer at R&D Altanova, recently presented an award winning presentation at the 2016 BITS workshop. “I’d like to congratulate Carol on winning the Attendee Choice Award. Being selected by your industry peers for best presentation is always a great honor,” said R&D Altanova’s CEO, James Russell. This marks the third year in a row an R&D Altanova staff member has won an award at the annual Burn-in & Test workshop.
Carol McCuen’s Attendee Choice Award at BITS 2016
The presentation focused on the requirements for taking accurate VNA/PNA S-parameter measurements (DC to 50GHz) of an interconnect, representing only the “socket” and also showing how the measurement parameters in frequency can affect the results when transforming into the time domain.
The presentation also discussed the process of creating an accurate 3D Electromagnetic field model to predict any pin configuration the customer may need. Results from some of the recent laboratory measurements were also included in the presentation, including our 1.0mm (25×25 mil) Invisipins as well as our 0.65mm (16×16 mil) Invisipins.
You can find this presentation by accessing our White Papers & Presentations.